Groq delivers fast, efficient AI inference. Our LPU-based system powers GroqCloud™, giving businesses and developers the speed and scale they need. From our Bay Area roots to our growing global presence, we are on a mission to make high performance AI compute more accessible and affordable. When real-time AI is within reach, anything is possible. Build fast.

Staff DFT Engineer

Mission:

As a Staff DFT Engineer, you will be responsible to enable Groq’s next‑generation LPU by designing, integrating, and validating cutting‑edge DFT solutions.

Responsibilities & opportunities in this role:

Build & Own End‑to‑End DFT Flow: Design a production‑ready DFT flow from scratch, select tools from an industry‑leading EDA partner , create reusable templates, scripts, and best‑practice guidelines.
RTL DFT DRC & Optimization: Run DFT DRC on RTL blocks, propose fixes, and deliver RTL that meets timing, area, and power targets.
Timing Closure & Sign‑off: Write DFT‑specific timing constraints, work with physical design to close timing in test mode, and sign off test‑mode constraints.
Test Vector Development: Generate ATPG, IJTAG, and MBIST vectors; run RTL and gate‑level simulations to achieve high coverage and verify functional path exercise.
Post‑Silicon Bring‑up: Partner with silicon validation teams to run patterns on silicon, troubleshoot ATE issues, and streamline validation cycles.
Automation & Workflow Improvement: Identify bottlenecks, develop Tcl/Python automation, and integrate new tools to reduce manual effort and boost productivity.
Documentation & Knowledge Transfer: Maintain version‑controlled DFT documentation, create a “DFT playbook,” and lead knowledge‑sharing sessions.

Ideal candidates have/are:

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
8+ years of industry experience with Design for Test (DFT) for high-performance ASICs.
Proven hands‑on experience with industry‑leading DFT tools, techniques and methodologies for large SOC/ASIC designs.
Expert in core DFT techniques: ATPG, scan compression, MBIST, IJTAG, IEEE -1500, Logic BIST, test‑pattern translation, and yield learning.
Experience with UDFM’s such as Cell Aware and Small Delay Defect.
Experience in ATPG Streaming SCAN Network (SSN) implementation.
Strong timing‑analysis, constraint sign‑off, and gate‑level simulation skills; adept at debugging DFT patterns on real silicon and ATE.
Strong knowledge of RTL to GDS methodologies and formal equivalence.
Excellent coding skills in Tcl and Python.
Strong interpersonal and organizational skills.
Ability and desire to work effectively as part of a team.

Attributes of a Groqster:

Humility - Egos are checked at the door
Collaborative & Team Savvy - We make up the smartest person in the room, together
Growth & Giver Mindset - Learn it all versus know it all, we share knowledge generously
Curious & Innovative - Take a creative approach to projects, problems, and design
Passion, Grit, & Boldness - no limit thinking, fueling informed risk taking

Compensation: At Groq, a competitive base salary is part of our comprehensive compensation package, which includes equity and benefits. For this role, the base salary range is $170,000 to $205,000, determined by your location, skills, qualifications, experience and internal benchmarks. This range is specific to roles in the United States, compensation for candidates outside the USA will be dependent on the local market.

Groq is an Equal Opportunity Employer. We are committed to creating an inclusive environment for all employees and applicants. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, sex (including gender identity, sexual orientation, and pregnancy), age, disability, genetic information, protected veteran status, or any other characteristic protected by applicable law.

Groq complies with all applicable federal, state, and local laws governing nondiscrimination in employment. We do not tolerate discrimination or harassment based on any protected characteristic.

Groq is committed to working with and providing reasonable accommodations to qualified individuals with physical or mental disabilities. If you require a reasonable accommodation to complete an application or to participate in the hiring process, please contact us at talent@groq.com. This contact is for accommodation requests only, which will be considered on a case-by-case basis.

All offers of employment are contingent upon verification of the applicant’s identity and employment authorization in accordance with federal law.

Groq encourages people with criminal record histories to apply for employment, and values diverse experiences, including prior contact with the criminal legal system. To that end, Groq welcomes such applicants in accordance with the California Fair Chance Act, Los Angeles City Fair Chance Act Ordinance, Los Angeles County Fair Chance Act Ordinance, and San Francisco Fair Chance Act Ordinance. Philadelphia applicants can review information pertaining to Philadelphia’s Fair Criminal Record Screening Standards Ordinance here: https://www.phila.gov/documents/fair-chance-hiring-law-poster.

Req ID: R581

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