• Build & Own End‑to‑End DFT Flow: Design a production‑ready DFT flow from scratch, select tools from an industry‑leading EDA partner , create reusable templates, scripts, and best‑practice guidelines.
• RTL DFT DRC & Optimization: Run DFT DRC on RTL blocks, propose fixes, and deliver RTL that meets timing, area, and power targets.
• Timing Closure & Sign‑off: Write DFT‑specific timing constraints, work with physical design to close timing in test mode, and sign off test‑mode constraints.
• Test Vector Development: Generate ATPG, IJTAG, and MBIST vectors; run RTL and gate‑level simulations to achieve high coverage and verify functional path exercise.
• Post‑Silicon Bring‑up: Partner with silicon validation teams to run patterns on silicon, troubleshoot ATE issues, and streamline validation cycles.
• Automation & Workflow Improvement: Identify bottlenecks, develop Tcl/Python automation, and integrate new tools to reduce manual effort and boost productivity.
• Documentation & Knowledge Transfer: Maintain version‑controlled DFT documentation, create a “DFT playbook,” and lead knowledge‑sharing sessions.

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• 8+ years of industry experience with Design for Test (DFT) for high-performance ASICs.
• Proven hands‑on experience with industry‑leading DFT tools, techniques and methodologies for large SOC/ASIC designs.
• Expert in core DFT techniques: ATPG, scan compression, MBIST, IJTAG, IEEE -1500, Logic BIST, test‑pattern translation, and yield learning.
• Experience with UDFM’s such as Cell Aware and Small Delay Defect.
• Experience in ATPG Streaming SCAN Network (SSN) implementation.
• Strong timing‑analysis, constraint sign‑off, and gate‑level simulation skills; adept at debugging DFT patterns on real silicon and ATE.
• Strong knowledge of RTL to GDS methodologies and formal equivalence.
• Excellent coding skills in Tcl and Python.
• Strong interpersonal and organizational skills.
• Ability and desire to work effectively as part of a team.

• Humility - Egos are checked at the door
• Collaborative & Team Savvy - We make up the smartest person in the room, together
• Growth & Giver Mindset - Learn it all versus know it all, we share knowledge generously
• Curious & Innovative - Take a creative approach to projects, problems, and design
• Passion, Grit, & Boldness - no limit thinking, fueling informed risk taking

Compensation: At Groq, a competitive base salary is part of our comprehensive compensation package, which includes equity and benefits. For this role, the base salary range is $170,000 to $205,000, determined by your location, skills, qualifications, experience and internal benchmarks. This range is specific to roles in the United States, compensation for candidates outside the USA will be dependent on the local market.